Apb1 Peripheral Reset Register (Rcc_Apb1Rstr) - STMicroelectronics RM0365 Reference Manual

RM0365
9.4.5

APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
I2C3 DAC1 PWR
Res
RST RST RST
rw rw
15 14 13
SPI3 SPI2
Res Res
RST RST
rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 I2C3RST: I2C3 reset
Set and cleared by software.
Bit 29 DAC1RST: DAC1 interface reset
Set and cleared by software.
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
Bits 27:26 Reserved, must be kept at reset value.
Bit 25 CANRST: CAN reset
Set and reset by software.
Bit 24 Reserved, must be kept at reset value
Bit 23 USBRST: USB reset
Set and reset by software.
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
28 27 26 25
CAN
Res Res
RST
rw rw
12 11 10 9
WWDG
Res Res
RST
rw
0: No effect
1: Reset I2C3
0: No effect
1: Reset DAC1 interface
0: No effect
1: Reset power interface
0: does not reset the CAN
1: resets the CAN
0: does not reset USB
1: resets USB
0: No effect
1: Reset I2C2
0: No effect
1: Reset I2C1
24 23 22
I2C2
USB
Res
RST
RST
rw rw
8 7 6
Res Res Res
DocID025202 Rev 7
Reset and clock control (RCC)
21 20 19 18
I2C1 UART5 UART4 USART3
RST RST RST RST
rw rw rw rw
5 4 3 2
TIM6 TIM4
Res Res
RST RST
rw rw
17 16
USART2
Res
RST
rw
1 0
TIM3 TIM2
RST RST
rw rw
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