Table 67. Fmc_Bcrx Bit Fields; Figure 43. Muxed Write Access Waveforms - STMicroelectronics RM0365 Reference Manual

RM0365
The difference with mode D is the drive of the lower address byte(s) on the data bus.
Bit No.
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2

Figure 43. Muxed write access waveforms

Table 67. FMC_BCRx bit fields

Bit name
Reserved 0x000
CCLKEN As needed
CBURSTRW 0x0 (no effect in asynchronous mode)
Reserved 0x0
Set to 1 if the memory supports this feature. Otherwise keep at
ASYNCWAIT
0.
EXTMOD 0x0
WAITEN 0x0 (no effect in asynchronous mode)
WREN As needed
WAITCFG Don't care
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN 0x1
MWID As needed
MTYP 0x2 (NOR Flash memory)
DocID025202 Rev 7
Flexible static memory controller (FSMC)
Value to set
252/1080
286