Debug Mode; I2C Low-Power Modes; I2C Interrupts; Table 149. Low-Power Modes - STMicroelectronics RM0365 Reference Manual

RM0365
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter.
•
In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
•
If SMBus is supported (see
managed with the NBYTES counter. Refer to
SMBus Master receiver on page
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
28.4.17

Debug mode

When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT
configuration bits in the DBG module.
28.5

I2C low-power modes

Mode
Sleep
Stop
Standby The I2C peripheral is powered down and must be reinitialized after exiting Standby.
28.6

I2C interrupts

The table below gives the list of I2C interrupt requests.
Receive buffer not empty
Transmit buffer interrupt status
Stop detection interrupt flag
Transfer Complete Reload
Transfer complete
Address matched
NACK reception

Table 149. low-power modes

No effect
I2C interrupts cause the device to exit the Sleep mode.
The contents of I2C registers are kept.

Table 150. I2C Interrupt requests

Interrupt event
DocID025202 Rev 7
Inter-integrated circuit (I2C) interface
Section 28.3: I2C implementation): the PEC transfer is
SMBus Slave receiver on page 807
811.
Description
Event flag/Interrupt
Event flag
RXNE
TXIS
STOPF
Write I2C_CR2 with
TCR
Write START=1 or
TC
ADDR Write ADDRCF=1
NACKF
Interrupt enable
clearing method
Read I2C_RXDR
register
Write I2C_TXDR
register
Write STOPCF=1
NBYTES[7:0] ≠ 0
STOP=1
Write NACKCF=1
and
control bit
RXIE
TXIE
STOPIE
TCIE
ADDRIE
NACKIE
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