Clock Interrupt Register (Rcc_Cir) - STMicroelectronics RM0365 Reference Manual

RM0365
9.4.3

Clock interrupt register (RCC_CIR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res Res Res Res
15 14 13
PLL
Res Res Res
RDYIE
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
Bits 22:21 Reserved, must be kept at reset value.
Bit 20 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
28 27 26 25
Res Res Res
12 11 10 9
HSE HSI LSE
RDYIE RDYIE RDYIE
rw rw rw rw
0: No effect
1: Clear CSSF flag
0: No effect
1: Clear PLLRDYF flag
0: No effect
1: Clear HSERDYF flag
0: No effect
1: Clear HSIRDYF flag
0: No effect
1: LSERDYF cleared
0: No effect
1: LSIRDYF cleared
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
DocID025202 Rev 7
24 23 22 21
Res CSSC Res Res
w
8 7 6
LSI
CSSF Res Res
RDYIE
rw r
Reset and clock control (RCC)
20 19 18
PLL HSE HSI
RDYC RDYC RDYC
w w w
5 4 3 2
PLL HSE HSI
RDYF RDYF RDYF
r r r
17 16
LSE LSI
RDYC RDYC
w w
1 0
LSE LSI
RDYF RDYF
r r
132/1080
154