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RM0365
26.4
IWDG registers
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
26.4.1
Key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
31
30
29
Res.
Res.
Res.
Res.
15
14
13
w
w
w
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000)
These bits must be written by software at regular intervals with the key value 0xAAAA,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and
IWDG_WINR registers (see
Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is
selected)
Section 2.1 on page 42
28
27
26
25
Res.
Res.
Res.
12
11
10
9
w
w
w
w
for a list of abbreviations used in register descriptions.
24
23
22
Res.
Res.
Res.
8
7
6
KEY[15:0]
w
w
w
Section 26.3.5: Register access
DocID025202 Rev 7
Independent watchdog (IWDG)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
w
w
w
w
protection)
17
16
Res.
Res.
1
0
w
w
716/1080
721
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