Spi Data Register (Spix_Dr); Spi Crc Polynomial Register (Spix_Crcpr) - STMicroelectronics RM0365 Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
Bit 4 CRCERR: CRC error flag
This flag is set by hardware and cleared by software writing 0.
Note: This bit is not used in I
Bit 3 UDR: Underrun flag
0: No underrun occurred
1: Underrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
page 945
Note: This bit is not used in SPI mode.
Bit 2 CHSIDE: Channel side
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
Note: This bit is not used in SPI mode. It has no significance in PCM mode.
Bit 1 TXE: Transmit buffer empty
Bit 0 RXNE: Receive buffer not empty
30.9.4

SPI data register (SPIx_DR)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 DR[15:0]: Data register
Data received or to be transmitted
The data register serves as an interface between the Rx and Tx FIFOs. When the data
register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See
Section 30.5.9: Data transmission and reception
Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and
30.9.5

SPI CRC polynomial register (SPIx_CRCPR)

Address offset: 0x10
Reset value: 0x0007
15 14 13
rw rw rw
953/1080
0: CRC value received matches the SPIx_RXCRCR value
1: CRC value received does not match the SPIx_RXCRCR value
for the software sequence.
0: Tx buffer not empty
1: Tx buffer empty
0: Rx buffer empty
1: Rx buffer not empty
12 11 10 9
rw rw rw rw
read as zero when the register is read. The Rx threshold setting must always
correspond with the read access currently used.
12 11 10 9
rw rw rw rw
2
S mode.
8 7 6
DR[15:0]
rw rw rw
procedures).
8 7 6
CRCPOLY[15:0]
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DocID025202 Rev 7
I2S error flags on
5 4 3 2
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5 4 3 2
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RM0365
1 0
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1 0
rw rw