Dac Trigger Selection; Table 100. External Triggers (Dac1) - STMicroelectronics RM0365 Reference Manual

Digital-to-analog converter (DAC1)
Note: (V is replaced by V
REF+
16.5.4

DAC trigger selection

If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which possible
events will trigger conversion as shown in
TIM6_TRGO event
TIM3_TRGO event
Reserved
TIM15_TRGO event
TIM2_TRGO event
TIM4_TRGO event
EXTI line9
SWTRIG
1. To select TIM3_TRGO event as DAC1 trigger source, the DAC_ TRIG_RMP bit must be set in
SYSCFG_CFGR1 register.
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is
selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only
one APB1 clock cycle.
397/1080
on the 64-, 49-, 48- and 32-pin packages)
DDA

Table 100. External triggers (DAC1)

Source
(1)
Internal signal from on-chip
timers
External pin
Software control bit
DocID025202 Rev 7
Table 100.
Type
RM0365
TSEL[2:0]
000
001
010
011
100
101
110
111