External Memory Interface Signals; Table 73. Programmable Nand Flash/Pc Card Access Parameters; Table 74. 8-Bit Nand Flash - STMicroelectronics RM0365 Reference Manual

RM0365
Parameter
Memory setup
time
Memory wait
Memory hold
Memory
databus high-Z
14.6.1

External memory interface signals

The following tables list the signals that are typically used to interface NAND Flash memory
and PC Card.
Note: The prefix "N" identifies the signals which are active low.
8-bit NAND Flash memory
t
FMC signal name
NOE(= NRE)
NWAIT/INT[3:2]
Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.

Table 73. Programmable NAND Flash/PC Card access parameters

Function
Number of clock cycles (HCLK)
required to set up the address
before the command assertion
Minimum duration (in HCLK clock
cycles) of the command assertion
Number of clock cycles (HCLK)
during which the address must be
held (as well as the data if a write
access is performed) after the
command de-assertion
Number of clock cycles (HCLK)
during which the data bus is kept
in high-Z state after a write
access has started
I/O
A[17] O
A[16] O
D[7:0] I/O
NCE[x] O
O
NWE O
I
DocID025202 Rev 7
Flexible static memory controller (FSMC)
Access mode
Read/Write
Read/Write
Read/Write

Table 74. 8-bit NAND Flash

NAND Flash address latch enable (ALE) signal
NAND Flash command latch enable (CLE) signal
8-bit multiplexed, bidirectional address/data bus
Chip Select, x = 2, 3
Output enable (memory signal name: read enable, NRE)
Write enable
NAND Flash ready/busy input signal to the FMC
Unit
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
Write
(HCLK)
Function
Min. Max.
1 255
2 256
1 254
0 255
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