Direct memory access controller (DMA)
1. TIM16_CH1, TIM16_UP, TIM17_CH1, TIM17_UP and DMA request are mapped on this DMA channel only
if the corresponding remapping bit is set in the SYSCFG_CFGR1 or SYSCFG_CFGR3 register. For more
details, please refer to
191/1080
Figure 25. STM32F302x6/8 DMA1 request mapping
Section 11.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page
DocID025202 Rev 7
RM0365
172.
Need help?
Do you have a question about the RM0365 and is the answer not in the manual?
Questions and answers