Control/Status Register (Rcc_Csr) - STMicroelectronics RM0365 Reference Manual

Reset and clock control (RCC)
Bit 2 LSEBYP: LSE oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the
LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.
0: LSE oscillator not ready
1: LSE oscillator ready
Bit 0 LSEON: LSE oscillator enable
Set and cleared by software.
0: LSE oscillator OFF
1: LSE oscillator ON
9.4.10

Control/status register (RCC_CSR)

Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0
Wait states are inserted in case of successive accesses to this register.
31 30 29
IW
LPWR WWDG
WDG
RSTF RSTF RSTF
RSTF
15 14 13
Res Res Res
Bit 31 LPWRSTF: Low-power reset flag
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on low-power management reset, refer to Reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
145/1080
wait state 3, word, half-word and byte access
≤ ≤
28 27 26 25
SFT POR PIN
OB
LRSTF
RSTF RSTF
12 11 10 9
Res Res Res Res
24 23 22
V18PW
RMVF Res
RRSTF
8 7 6
Res Res Res
DocID025202 Rev 7
21 20 19 18
Res Res Res Res
5 4 3 2
Res Res Res Res
RM0365
17 16
Res Res
1 0
LSI
LSION
RDY
r rw