External Device Address Mapping - STMicroelectronics RM0365 Reference Manual

RM0365
Therefore, some simple transaction rules must be followed:
•
AHB transaction size and memory data size are equal
There is no issue in this case.
•
AHB transaction size is greater than the memory size:
In this case, the FMC splits the AHB transaction into smaller consecutive memory
accesses to meet the external data width. The FMC Chip Select (FMC_NEx) does not
toggle between the consecutive accesses.
•
AHB transaction size is smaller than the memory size:
The transfer may or not be consistent depending on the type of external device:
–
–
Configuration registers
The FMC can be configured through a set of registers. Refer to
detailed description of the NOR Flash/PSRAM controller registers. Refer to
for a detailed description of the NAND Flash/PC Card registers.
14.4

External device address mapping

From the FMC point of view, the external memory is divided into fixed-size banks of
256 Mbytes each (see
•
Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is
split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows:
–
–
–
–
• Banks 2 and 3 used to address NAND Flash memory devices (1 device per bank)
•
Bank 4 used to address a PC Card
For each bank the type of memory to be used can be configured by the user application
through the Configuration register.
Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM)
In this case, the FMC allows read/write transactions and accesses the right data
through its byte lanes NBL[1:0].
Bytes to be written are addressed by NBL[1:0].
All memory bytes are read (NBL[1:0] are driven low during read transaction) and
the useless ones are discarded.
Accesses to devices that do not have the byte select feature (NOR and NAND
Flash memories)
This situation occurs when a byte access is requested to a 16-bit wide Flash
memory. Since the device cannot be accessed in byte mode (only 16-bit words
can be read/written from/to the Flash memory), Write transactions and Read
transactions are allowed (the controller reads the entire 16-bit memory word and
uses only the required byte).
Figure 30):
Bank 1 - NOR/PSRAM 1
Bank 1 - NOR/PSRAM 2
Bank 1 - NOR/PSRAM 3
Bank 1 - NOR/PSRAM 4
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