Nand Flash / Pc Card Supported Memories And Transactions; Timing Diagrams For Nand Flash Memory And Pc Card; Table 77. Supported Memories And Transactions - STMicroelectronics RM0365 Reference Manual

RM0365
14.6.2

NAND Flash / PC Card supported memories and transactions

Table 77
allowed (or not supported) by the NAND Flash / PC Card controller are shown in gray.
Device
NAND 8-bit
NAND 16-bit
14.6.3

Timing diagrams for NAND Flash memory and PC Card

Each PC Card/CompactFlash and NAND Flash memory bank is managed through a set of
registers:
•
Control register: FMC_PCRx
• Interrupt status register: FMC_SRx
•
ECC register: FMC_ECCRx
• Timing register for Common memory space: FMC_PMEMx
•
Timing register for Attribute memory space: FMC_PATTx
• Timing register for I/O space: FMC_PIOx
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access,
plus one parameter that defines the timing for starting driving the data bus when a write
access is performed.
accesses, knowing that Attribute and I/O (only for PC Card) memory space access timings
are similar.
shows the supported devices, access modes and transactions. Transactions not

Table 77. Supported memories and transactions

Mode R/W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Figure 49
DocID025202 Rev 7
Flexible static memory controller (FSMC)
AHB Memory
data size data size
8 8
8 8
16 8
16 8
32 8
32 8
8 16
8 16
16 16
16 16
32 16
32 16
shows the timing parameter definitions for common memory
Allowed/
Comments
not allowed
Y
Y
Y Split into 2 FMC accesses
Y Split into 2 FMC accesses
Y Split into 4 FMC accesses
Y Split into 4 FMC accesses
Y
N
Y
Y
Y Split into 2 FMC accesses
Y Split into 2 FMC accesses
-
-
-
-
-
-
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