Table of Contents
Advertisement
Interrupts and events
Bits 31:1 Reserved, must be kept at reset value.
Note:
The external wakeup lines are edge-triggered. No glitches must be generated on these
lines. If a falling edge on an external interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.r
13.3.11
Software interrupt event register (EXTI_SWIER2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
13.3.12
Pending register (EXTI_PR2)
Address offset: 0x34
Reset value: undefined
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
223/1080
Bit 0 TRx: Falling trigger event configuration bit of line x (x = 32)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 0 SWIERx: Software interrupt on line x (x = 32)
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when
it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1' to
the bit).
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
DocID025202 Rev 7
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0365
17
16
Res.
Res.
1
0
SWIER
Res.
32
rw
17
16
Res.
Res.
1
0
Res.
PR32
rc_w1
Advertisement
Table of Contents
Need help?
Do you have a question about the RM0365 and is the answer not in the manual?
Questions and answers