Dma Channel X Memory Address Register (Dma_Cmarx) (X = 1 - STMicroelectronics RM0365 Reference Manual

Direct memory access controller (DMA)
12.5.6

DMA channel x memory address register (DMA_CMARx) (x = 1..7,

where x = channel number)
Address offset: 0x14 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 MA[31:0]: Memory address
Base address of the memory area from/to which the data will be read/written.
When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-
word address.
When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word
address.
201/1080
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
DocID025202 Rev 7
24 23 22 21
MA [31:16]
rw rw rw rw
8 7 6 5
MA [15:0]
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
RM0365
16
rw
0
rw