Clock Configuration Register 2 (Rcc_Cfgr2) - STMicroelectronics RM0365 Reference Manual

RM0365
Bit 18 IOPBRST: I/O port B reset
Set and cleared by software.
0: No effect
1: Reset I/O port B
Bit 17 IOPARST: I/O port A reset
Set and cleared by software.
0: No effect
1: Reset I/O port A
Bit 16 IOPHRST: I/O port H reset (Only on STM32F302xDxE).
Set and cleared by software.
0: No effect
1: Reset I/O port H
Bits 15:6 Reserved, must be kept at reset value.
Bit 5 FMCRST: FMC reset (Only on STM32F302xDxE).
Set and cleared by software.
0: No effect
1: Reset FMC
Bits 4:0 Reserved, must be kept at reset value.
9.4.12

Clock configuration register 2 (RCC_CFGR2)

Address: 0x2C
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31 30 29
Res Res Res
15 14 13
Res Res Res
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
24 23 22
Res Res Res
8 7 6
ADC12PRES[4:0]
rw rw rw
DocID025202 Rev 7
Reset and clock control (RCC)
21 20 19 18
Res Res Res Res
5 4 3 2
PREDIV[3:0]
rw rw rw rw
17 16
Res Res
1 0
rw rw
148/1080
154