Reload Register (Iwdg_Rlr) - STMicroelectronics RM0365 Reference Manual

RM0365
26.4.3

Reload register (IWDG_RLR)

Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 RL[11:0]: Watchdog counter reload value
These bits are write access protected see
are written by software to define the value to be loaded in the watchdog counter each time the
value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from
this value. The timeout period is a function of this value and the clock prescaler. Refer to the
datasheet for the timeout information.
The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw
may not be up to date/valid if a write operation to this register is ongoing on this
register. For this reason the value read from this register is valid only when the RVU bit
in the IWDG_SR register is reset.
DocID025202 Rev 7
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
RL[11:0]
rw rw rw rw
Section 26.3.5: Register access
Independent watchdog (IWDG)
20 19 18
Res. Res. Res.
4 3 2
rw rw rw
protection. They
17 16
Res. Res.
1 0
rw rw
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