Spi Interrupts; Table 163. Spi Interrupt Requests - STMicroelectronics RM0365 Reference Manual

RM0365
If the SPI is disabled during a communication the following sequence must be followed:
1. Disable the SPI
2. Clear the CRCEN bit
3. Enable the CRCEN bit
4. Enable the SPI
Note: When the SPI is in slave mode, the CRC calculator is sensitive to the SCK slave input clock
as soon as the CRCEN bit is set, and this is the case whatever the value of the SPE bit. In
order to avoid any wrong CRC calculation, the software must enable CRC calculation only
when the clock is stable (in steady state).
When the SPI interface is configured as a slave, the NSS internal signal needs to be kept
low during transaction of the CRC phase once the CRCNEXT signal is released. That is why
the CRC calculation can't be used at NSS Pulse mode when NSS hardware mode should
be applied at slave normally (see more details at the product errata sheet).
At TI mode, despite the fact that clock phase and clock polarity setting is fixed and
independent on SPIx_CR1 register, the corresponding setting CPOL=0 CPHA=1 has to be
kept at the SPIx_CR1 register anyway if CRC is applied. In addition, the CRC calculation
has to be reset between sessions by SPI disable sequence with re-enable the CRCEN bit
described above at both master and slave side, else CRC calculation can be corrupted at
this specific mode.
30.6

SPI interrupts

During SPI communication an interrupts can be generated by the following events:
• Transmit TXFIFO ready to be loaded
•
Data received in Receive RXFIFO
• Master mode fault
•
Overrun error
• TI frame format error
•
CRC protocol error
Interrupts can be enabled and disabled separately.
Transmit TXFIFO ready to be loaded
Data received in RXFIFO
Master Mode fault event
Overrun error
TI frame format error
CRC protocol error
Serial peripheral interface / inter-IC sound (SPI/I2S)

Table 163. SPI interrupt requests

Interrupt event
DocID025202 Rev 7
Event flag Enable Control bit
TXE
RXNE
MODF
OVR
FRE
CRCERR
TXEIE
RXNEIE
ERRIE
928/1080
959