Single Conversion Mode (Cont=0); Continuous Conversion Mode (Cont=1) - STMicroelectronics RM0365 Reference Manual

RM0365
Constraints on the sampling time for fast and slow channels
For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time
as specified in the ADC charateristics section of the datasheets.
15.3.13

Single conversion mode (CONT=0)

In Single conversion mode, the ADC performs once all the conversions of the channels.
This mode is started with the CONT bit at 0 by either:
•
Setting the ADSTART bit in the ADCx_CR register (for a regular channel)
•
Setting the JADSTART bit in the ADCx_CR register (for an injected channel)
•
External hardware trigger event (for a regular or injected channel)
Inside the regular sequence, after each conversion is complete:
•
The converted data are stored into the 16-bit ADCx_DR register
•
The EOC (end of regular conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
Inside the injected sequence, after each conversion is complete:
•
The converted data are stored into one of the four 16-bit ADCx_JDRy registers
•
The JEOC (end of injected conversion) flag is set
•
An interrupt is generated if the JEOCIE bit is set
After the regular sequence is complete:
•
The EOS (end of regular sequence) flag is set
•
An interrupt is generated if the EOSIE bit is set
After the injected sequence is complete:
•
The JEOS (end of injected sequence) flag is set
•
An interrupt is generated if the JEOSIE bit is set
Then the ADC stops until a new external regular or injected trigger occurs or until bit
ADSTART or JADSTART is set again.
Note: To convert a single channel, program a sequence with a length of 1.
15.3.14

Continuous conversion mode (CONT=1)

This mode applies to regular channels only.
In continuous conversion mode, when a software or hardware regular trigger event occurs,
the ADC performs once all the regular conversions of the channels and then automatically
re-starts and continuously converts each conversions of the sequence. This mode is started
with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the
ADCx_CR register.
Inside the regular sequence, after each conversion is complete:
•
The converted data are stored into the 16-bit ADCx_DR register
• The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
DocID025202 Rev 7
Analog-to-digital converters (ADC)
302/1080
392