Table 68. Fmc_Btrx Bit Fields - STMicroelectronics RM0365 Reference Manual

Flexible static memory controller (FSMC)
Bit No.
1
0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
WAIT management in asynchronous accesses
If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles
before the end of the memory transaction. The following cases must be considered:
253/1080
Table 67. FMC_BCRx bit fields (continued)
Bit name
MUXEN 0x1
MBKEN 0x1

Table 68. FMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles for
DATAST
read accesses and DATAST+1 HCLK cycles for write accesses).
ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET
Minimum value for ADDSET is 1.
DocID025202 Rev 7
Value to set
Value to set
RM0365