STMicroelectronics RM0365 Reference Manual page 181

System configuration controller (SYSCFG)
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Bit 2 PVD_LOCK: PVD lock enable bit
This bit is set by software and cleared by a system reset. It can be used to
enable and lock the PVD connection to TIM1/15/16/17 Break input, as well as
the PVDE and PLS[2:0] in the PWR_CR register.
0: PVD interrupt disconnected from TIM1/15/16/17 Break input. PVDE and
PLS[2:0] bits can be programmed by the application.
1: PVD interrupt connected to TIM1/15/16/17 Break input, PVDE and PLS[2:0]
bits are read only.
Bit 1 SRAM_PARITY_LOCK: SRAM parity lock bit (STM32F302xB/C/D/E devices only)
This bit is set by software and cleared by a system reset. It can be used to
enable and lock the SRAM parity error signal connection to TIM1/15/16/17 Break
inputs.
0: SRAM parity error signal disconnected from TIM1/15/16/17 Break inputs
1: SRAM parity error signal connected to TIM1/15/16/17 Break inputs
Bit 0 LOCKUP_LOCK: Cortex
This bit is set by software and cleared by a system reset. It can be use to enable
and lock the connection of Cortex
TIM1/15/16/17 Break input.
®
0: Cortex -M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs.
®
1: Cortex -M4 LOCKUP output connected to TIM1/15/16/17 Break inputs
DocID025202 Rev 7
®
-M4 LOCKUP (Hardfault) output enable bit
®
-M4 LOCKUP (Hardfault) output to
RM0365