Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr) - STMicroelectronics RM0365 Reference Manual

Reset and clock control (RCC)
Bit 15 SPI4EN: SPI4 clock enable (STM32F302xD/E only)
Set and cleared by software.
0: SPI4 clock disabled
1: SPI4 clock enabled
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable (STM32F302xB/C devices only)
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG clock enable
Set and cleared by software.
0: SYSCFG clock disabled
1: SYSCFG clock enabled
9.4.8

APB1 peripheral clock enable register (RCC_APB1ENR)

Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29 28
I2C3 DAC1 PWR
Res
EN EN EN
rw rw rw
15 14 13 12
SPI3 SPI2
Res Res
EN EN
rw rw
141/1080
27 26 25 24
CAN
Res Res Res
EN
rw
11 10 9 8
WWD
Res Res Res
GEN
rw
DocID025202 Rev 7
23 22 21 20
USB I2C2 I2C1 UART5
EN EN EN EN
rw rw rw rw
7 6 5 4
Res Res Res TIM6EN
rw
RM0365
19 18 17
UART4 USART3 USART2
EN EN EN
rw rw rw
3 2 1
Res TIM4EN TIM3EN
rw rw
16
Res
0
TIM2
EN
rw