Figure 370. Operations Required To Receive 0X3478Ae; Figure 371. Lsb Justified 16-Bit Extended To 32-Bit Packet Frame; Figure 372. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame - STMicroelectronics RM0365 Reference Manual

Advanced arm-based 32-bit mcus
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RM0365
Serial peripheral interface / inter-IC sound (SPI/I2S)

Figure 370. Operations required to receive 0x3478AE

Figure 371. LSB justified 16-bit extended to 32-bit packet frame

2
When 16-bit data frame extended to 32-bit channel frame is selected during the I
S
configuration phase, Only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it
corresponds to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in
Figure 372
is required.

Figure 372. Example of 16-bit data frame extended to 32-bit channel frame

In transmission mode, when a TXE event occurs, the application has to write the data to be
transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).
The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and
not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun
or overrun conditions.
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