Adc Injected Data Register (Adcx_Jdry, X=1; Adc Analog Watchdog 2 Configuration Register - STMicroelectronics RM0365 Reference Manual

Analog-to-digital converters (ADC)
15.5.17

ADC injected data register (ADCx_JDRy, x=1

Address offset: 0x80 - 0x8C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data
15.5.18 ADC Analog Watchdog 2 Configuration Register (ADCx_AWD2CR,
x=1 2)
..
Address offset: 0xA0
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:1 AWD2CH[18:1]: Analog watchdog 2 channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by the analog watchdog 2.
AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2
AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2
When AWD2CH[18:1] = 000..0, the analog Watchdog 2 is disabled
Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers.
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 0 Reserved, must be kept at reset value.
381/1080
27 26 25
Res. Res. Res.
11 10 9
r r r r
These bits are read-only. They contain the conversion result from injected channel y. The
data are left -or right-aligned as described in
28 27 26 25
Res. Res. Res.
12 11 10 9
AWD2CH[15:1]
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
JDATA[15:0]
r r r
Section 15.3.26: Data
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
DocID025202 Rev 7
2, y= 1..4)
..
21 20 19 18
Res. Res. Res. Res.
5 4 3
r r r
management.
21 20 19 18
Res. Res. Res.
rw
5 4 3 2
rw rw rw rw
RM0365
17 16
Res. Res.
2 1 0
r r r
17 16
AWD2CH[18:16]
rw rw
1 0
Res.
rw