Syscfg External Interrupt Configuration Register 1; (Syscfg_Exticr1) - STMicroelectronics RM0365 Reference Manual

Advanced arm-based 32-bit mcus
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RM0365
Bit 11 TIM16_DMA_RMP: TIM16 DMA request remapping bit
This bit is set and cleared by software. It controls the remapping of TIM16 DMA request.
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADC2_DMA_RMP: ADC2 DMA remapping bit (STM32F302xB/C/D/E devices only)
This bit is set and cleared by software. It controls the remapping of ADC24 DMA requests.
Bit 7 DAC1_TRIG_RMP: DAC trigger remap (when TSEL = 001) (STM32F302xB/C/D/E devices
only)
This bit is set and cleared by software. It controls the mapping of the DAC trigger source.
Bit 6 TIM1_ITR3_RMP: Timer 1 ITR3 selection
This bit is set and cleared by software. It controls the mapping of TIM1 ITR3.
Bits 5:3 Reserved, must be kept at reset value.
Bits 2:0 MEM_MODE: Memory mapping selection bits
This bit is set and cleared by software. It controls the memory internal mapping at address
0x0000 0000. After reset these bits take on the memory mapping selected by BOOT0 pin and
BOOT1 option bit.
11.1.2

SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)

Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
EXTI3[3:0]
rw
rw
rw
0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3)
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6)
0: No remap (ADC24 DMA requests mapped on DMA2 channels 1 and 2)
1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4)
0: No remap
1: Remap (DAC trigger is TIM3_TRGO)
0: No remap (TIM1_ITR3 = TIM4_TRGO in STM32F302xB/C/D/E devices)
1: Remap (TIM1_ITR3 = TIM17_OC)
0x0: Main Flash memory mapped at 0x0000 0000
001: System Flash memory mapped at 0x0000 0000
011: Embedded SRAM (on the D-Code bus) mapped at 0x0000 0000
1xx: FMC Bank (Only the first two banks) (Available on STM32F302xD/E only).
28
27
26
25
Res.
Res.
Res.
12
11
10
9
EXTI2[3:0]
rw
rw
rw
rw
System configuration controller (SYSCFG)
24
23
22
Res.
Res.
Res.
8
7
6
EXTI1[3:0]
rw
rw
rw
DocID025202 Rev 7
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
EXTI0[3:0]
rw
rw
rw
rw
17
16
Res.
Res.
1
0
rw
rw
174/1080
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