Spi Control Register 2 (Spix_Cr2) - STMicroelectronics RM0365 Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
Bit 2 MSTR: Master selection
Note: This bit should not be changed when communication is ongoing.
Bit1 CPOL: Clock polarity
Note: This bit should not be changed when communication is ongoing.
Bit 0 CPHA: Clock phase
Note: This bit should not be changed when communication is ongoing.
30.9.2

SPI control register 2 (SPIx_CR2)

Address offset: 0x04
Reset value: 0x0700
15 14 13 12
LDMA LDMA FRXT
Res.
_TX _RX H
rw rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 LDMA_TX: Last DMA transfer for transmission
This bit is used in data packing mode, to define if the total number of data to transmit by DMA
is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and
if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It
has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
Note: Refer to
Bit 13 LDMA_RX: Last DMA transfer for reception
Th
odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if
packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has
to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
Note: Refer to
Bit 12 FRXTH: FIFO reception threshold
This bit is used to set the threshold of the RXFIFO that triggers an RXNE event
949/1080
0: Slave configuration
1: Master configuration
This bit is not used in I
0: CK to 0 when idle
1: CK to 1 when idle
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
11 10 9
DS [3:0]
rw rw rw
0: Number of data to transfer is even
1: Number of data to transfer is odd
Procedure for disabling the SPI on page 914
This bit is not used in I²S mode.
is bit is used in data packing mode, to define if the total number of data to receive by DMA is
0: Number of data to transfer is even
1: Number of data to transfer is odd
Procedure for disabling the SPI on page 914
This bit is not used in I²S mode.
0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
2
S mode.
8 7 6
TXEIE RXNEIE ERRIE
rw rw rw
DocID025202 Rev 7
5 4 3 2
FRF NSSP SSOE
rw rw rw rw
if the CRCEN bit is set.
if the CRCEN bit is set.
RM0365
1 0
TXDMAEN RXDMAEN
rw rw