Interrupt Mask Register (Exti_Imr2); Event Mask Register (Exti_Emr2) - STMicroelectronics RM0365 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Interrupts and events

Bits 29:23 Reserved, must be kept at reset value.

Bits 22:0 PRx: Pending bit on line x (x = 22 to 0)

Interrupt mask register (EXTI_IMR2)

Address offset: 0x20

Reset value: 0xFFFF FFFE (See note below)

Bits 31:4 Reserved, must be kept at reset value

The reset value for the reserved lines is set to '1'.

Address offset: 0x24

Reset value: 0x0000 0000

Bit 31 Reserved, must be kept at reset value.

Bit 30 PRx: Pending bit on line x (x = 30)

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by writing a '1' to the bit.

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by writing a '1' to the bit.

Bits 3:2 MRx: Interrupt mask on external/internal line x, x = 34, 35

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Bit 1 Reserved, must be kept at reset value.

Bit 0 MRx: Interrupt mask on external/internal line x, x = 32

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

DocID025202 Rev 7

Do you have a question about the RM0365 and is the answer not in the manual?