I2C Implementation; I2C Functional Description; Table 136. Stm32F302Xx I2C Implementation - STMicroelectronics RM0365 Reference Manual

RM0365
The following additional features are also available depending on the product
implementation (see
•
SMBus specification rev 2.0 compatibility:
–
–
–
–
–
–
• PMBus rev 1.1 standard compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
•
Wakeup from Stop mode on address match.
28.3

I2C implementation

This manual describes the full set of features implemented in I2C1, I2C3 and I2C3., I2C2,
I2C3 and I2C4./I2C3.
7-bit addressing mode
10-bit addressing mode
Standard-mode (up to 100 kbit/s)
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Independent clock
SMBus
Wakeup from Stop mode
1. X = supported.
2. I2C3 is not available in STM32F302xB/C devices.
28.4

I2C functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1 MHz) I
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).
Section 28.3: I2C
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
Command and data acknowledge control
Address resolution protocol (ARP) support
Host and Device support
SMBus alert
Timeouts and idle condition detection

Table 136. STM32F302xx I2C implementation

(1)
I2C features
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
2
C bus.
implementation):
DocID025202 Rev 7
Inter-integrated circuit (I2C) interface
I2C1 I2C2
X X
X X
X X
X X
X X
X X
X X
X X
(2)
I2C3
X
X
X
X
X
X
X
X
766/1080
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