Smbus Initialization; Figure 307. Timeout Intervals For T - STMicroelectronics RM0365 Reference Manual

RM0365
Bus idle detection
A master can assume that the bus is free if it detects that the clock and data signals have
been high for t
timings)
This timing parameter covers the condition where a master has been dynamically added to
the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.
SMBus
28.4.11
This section is relevant only when SMBus feature is supported. Please refer to
I2C implementation.
In addition to I2C initialization, some other specific initialization must be done in order to
perform SMBus communication:
Received Command and Data Acknowledge control (Slave mode)
A SMBus receiver must be able to NACK each received command or data. In order to allow
ACK control in slave mode, the Slave Byte Control mode must be enabled by setting the
SBC bit in the I2C_CR1 register. Refer to
details.

Figure 307. Timeout intervals for t

greater than t
IDLE
HIGH
initialization
DocID025202 Rev 7
Inter-integrated circuit (I2C) interface
LOW:SEXT
. (refer to Table 140: I2C-SMBUS specification clock
,
MAX
Slave Byte Control mode on page 779
, t .
LOW:MEXT
Section 28.3:
for more
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