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Embedded Flash memory
4.5
Flash register description
The Flash memory registers have to be accessed by 32-bit words (half-word and byte
accesses are not allowed).
4.5.1
Flash access control register (FLASH_ACR)
Address offset: 0x00
Reset value: 0x0000 0030
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:6 Reserved, must be kept at reset value.
4.5.2
Flash key register (FLASH_KEYR)
Address offset: 0x04
Reset value: xxxx xxxx
These bits are all write-only and return a 0 when read.
31
30
29
w
w
w
15
14
13
w
w
w
Bits 31:0 FKEYR: Flash key
71/1080
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 5 PRFTBS: Prefetch buffer status
This bit provides the status of the prefetch buffer.
0: Prefetch buffer is disabled
1: Prefetch buffer is enabled
Bit 4 PRFTBE: Prefetch buffer enable
0: Prefetch is disabled
1: Prefetch is enabled
Bit 3 HLFCYA: Flash half cycle access enable
0: Half cycle is disabled
1: Half cycle is enabled
Bits 2:0 LATENCY[2:0]: Latency
These bits represent the ratio of the HCLK period to the Flash access time.
000: Zero wait state, if 0 < HCLK ≤ 24 MHz
001: One wait state, if 24 MHz < HCLK ≤ 48 MHz
010: Two wait sates, if 48 < HCLK ≤ 72 MHz
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
These bits represent the keys to unlock the Flash.
DocID025202 Rev 7
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
PRFT
Res.
Res.
Res.
BS
r
24
23
22
21
FKEYR[31:16]
w
w
w
w
8
7
6
5
FKEYR[15:0]
w
w
w
w
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
PRFT
HLF
LATENCY[2:0]
BE
CYA
rw
rw
rw
rw
20
19
18
17
w
w
w
w
4
3
2
1
w
w
w
w
RM0365
16
Res.
0
rw
16
w
0
w
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