Adc Interrupts; Table 94. Adc Interrupts Per Each Adc - STMicroelectronics RM0365 Reference Manual

Analog-to-digital converters (ADC)
15.4

ADC interrupts

For each ADC, an interrupt can be generated:
•
After ADC power-up, when the ADC is ready (flag ADRDY)
• On the end of any conversion for regular groups (flag EOC)
•
On the end of a sequence of conversion for regular groups (flag EOS)
• On the end of any conversion for injected groups (flag JEOC)
•
On the end of a sequence of conversion for injected groups (flag JEOS)
•
When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)
•
When the end of sampling phase occurs (flag EOSMP)
•
When the data overrun occurs (flag OVR)
•
When the injected sequence context queue overflows (flag JQOVF)
Separate interrupt enable bits are available for flexibility.
ADC ready
End of conversion of a regular group
End of sequence of conversions of a regular group
End of conversion of a injected group
End of sequence of conversions of an injected group
Analog watchdog 1 status bit is set
Analog watchdog 2 status bit is set
Analog watchdog 3 status bit is set
End of sampling phase
Overrun
Injected context queue overflows
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Table 94. ADC interrupts per each ADC

Interrupt event
DocID025202 Rev 7
Event flag Enable control bit
ADRDY ADRDYIE
EOC EOCIE
EOS EOSIE
JEOC JEOCIE
JEOS JEOSIE
AWD1 AWD1IE
AWD2 AWD2IE
AWD3 AWD3IE
EOSMP EOSMPIE
OVR OVRIE
JQOVF JQOVFIE
RM0365