STMicroelectronics RM0365 Reference Manual page 143

Reset and clock control (RCC)
Bit 17 USART2EN: USART2 clock enable
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable
Set and cleared by software.
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
Bits 10:5 Reserved, must be kept at reset value.
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
Bit 3 Reserved, must be kept at reset value.
Bit 2 TIM4EN: TIM4 timer clock enable (STM32F302xB/C/D/E devices only)
Set and cleared by software.
Bit 1 TIM3EN: TIM3 timer clock enable (STM32F302xB/C devices only)
Set and cleared by software.
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
143/1080
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
0: SPI3 clock disabled
1: SPI3 clock enabled
0: SPI2 clock disabled
1: SPI2 clock enabled
0: Window watchdog clock disabled
1: Window watchdog clock enabled
0: TIM6 clock disabled
1: TIM6 clock enabled
0: TIM4 clock disabled
1: TIM4 clock enabled
0: TIM3 clock disabled
1: TIM3 clock enabled
0: TIM2 clock disabled
1: TIM2 clock enabled
DocID025202 Rev 7
RM0365