STMicroelectronics RM0365 Reference Manual page 744

RM0365
Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz)
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Time-stamp event active edge
Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection
Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in
write protection on page
Caution: TSE must be reset when TSEDGE is changed to avoid spuriously setting of TSF.
0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
0: RTC_TS input rising edge generates a time-stamp event
1: RTC_TS input falling edge generates a time-stamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 2
(see note below)
729.
DocID025202 Rev 7
Real-time clock (RTC)
16
is added to the WUT counter value
RTC register
744/1080
764