Adc Control Register (Adcx_Cr, X=1 - STMicroelectronics RM0365 Reference Manual

RM0365
15.5.3

ADC control register (ADCx_CR, x=1

Address offset: 0x08
Reset value: 0x2000 0000
31 30 29
AD
ADCA
ADVREGEN[1:0]
LDIF
CAL
rs rw rw
15 14 13
Res. Res. Res. Res.
Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to
determine if this calibration applies for single-ended or differential inputs mode.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
Note: Software is allowed to launch a calibration by setting ADCAL only when ADEN=0.
Note: Software is allowed to update the calibration factor by writing ADCx_CALFACT only when
ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)
Bit 30 ADCALDIF: Differential mode for calibration
This bit is set and cleared by software to configure the single-ended or differential inputs mode for the
calibration.
0: Writing ADCAL will launch a calibration in Single-ended inputs Mode.
1: Writing ADCAL will launch a calibration in Differential inputs Mode.
Note: Software is allowed to write this bit only when the ADC is disabled and is not calibrating
(ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 29:28 ADVREGEN[1:0]: ADC voltage regulator enable
These bits are set by software to enable the ADC voltage regulator.
Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage
regulator must first be enabled and the software must wait for the regulator start-up time.
00: Intermediate state required when moving the ADC voltage regulator from the enabled to the
disabled state or from the disabled to the enabled state.
01: ADC Voltage regulator enabled.
10: ADC Voltage regulator disabled (Reset state)
11: reserved
For more details about the ADC voltage regulator enable and disable sequences, refer to
Section 15.3.6: ADC voltage regulator
Note: The software can program this bit field only when the ADC is disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 27:6 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
rw
12 11 10 9
Res. Res. Res.
DocID025202 Rev 7
Analog-to-digital converters (ADC)
2)
..
24 23 22 21
Res. Res. Res. Res.
8 7 6
JAD
Res. Res. Res.
STP
(ADVREGEN).
20 19 18
Res. Res. Res.
5 4 3 2
AD JAD AD
STP START START
rs rs rs rs
17 16
Res. Res.
1 0
AD AD
DIS EN
rs rs
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