Interrupts and events
13.2.2
Block diagram
The extended interrupt/event block diagram is shown in the following figure.
13.2.3
Wakeup event management
STM32F302xx devices are able to handle external or internal events in order to wake up the
core (WFE). The wakeup event can be generated either by:
•
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex
resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
•
or by configuring an external or internal EXTI line in event mode. When the CPU
resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is
not set.
13.2.4
Asynchronous Internal Interrupts
Some communication peripherals (UART, I2C) are able to generate events when the system
is in run mode and also when the system is in stop mode allowing to wake up the system
from stop mode.
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Figure 27. External interrupt/event block diagram
®
-M4 System Control register. When the MCU
DocID025202 Rev 7
RM0365
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