Comp Reset And Clocks; Comparator Lock Mechanism; Table 103. Stm32F302X6/8 Comparator Input/Outputs Summary - STMicroelectronics RM0365 Reference Manual

RM0365
Comparator inverting
Input: connection to
internal signals
Comparator Inputs
connected to I/Os
(+: non inverting input;
-: inverting input)
Comparator outputs
(motor control
protection)
Outputs on I/Os
Outputs to internal
signals
17.3.3

COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the PCLK2 (APB2
clock).
There is no clock enable control bit provided in the RCC controller. To use a clock source for
the comparator, the SYSCFG clock enable control bit must be set in the RCC controller.
Note: Important: The polarity selection logic and the output redirection to the port works
independently from the PCLK2 clock. This allows the comparator to work even in Stop
mode.
17.3.4

Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to
insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.

Table 103. STM32F302x6/8 comparator input/outputs summary

COMP2
+: PA7
-: PA2
-: PA4
PA2
PA12
PB12
TIM1_OCREF_CLR
TIM1_IC1
TIM2_IC4
TIM2_OCREF_CLR
DocID025202 Rev 7
Comparator input/outputs
COMP4
DAC1_CH1
Vrefint
¾ Vrefint
½ Vrefint
¼ Vrefint
+: PB0
-: PB2
-: PA4
T1BKIN
T1BKIN2
PB1
TIM15_OCREF_CLR
TIM15_IC2
Comparator (COMP)
COMP6
+: PB11
-: PB15
-: PA4
PA10
PC6
TIM2_IC2
TIM2_OCREF_CLR
TIM16_OCREF_CLR
TIM16_IC1
410/1080
422