Baud Rate Register (Usart_Brr); Guard Time And Prescaler Register (Usart_Gtpr) - STMicroelectronics RM0365 Reference Manual

RM0365
29.8.4

Baud rate register (USART_BRR)

This register can only be written when the USART is disabled (UE=0). It may be
automatically updated by hardware in auto baud rate detection mode.
Address offset: 0x0C
Reset value: 0x0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 BRR[15:4]
Bits 3:0 BRR[3:0]
29.8.5

Guard time and prescaler register (USART_GTPR)

Address offset: 0x10
Reset value: 0x0000
31 30 29
Res. Res. Res. Res.
15 14 13
Universal synchronous asynchronous receiver transmitter (USART)
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
BRR[15:4] = USARTDIV[15:4]
When OVER8 = 0, BRR[3:0] = USARTDIV[3:0].
When OVER8 = 1:
BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
BRR[3] must be kept cleared.
28 27 26 25
Res. Res. Res.
12 11 10 9
GT[7:0]
rw
DocID025202 Rev 7
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
BRR[15:0]
rw rw rw rw
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
rw rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
PSC[7:0]
rw
16
Res.
0
rw
16
Res.
0
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