STMicroelectronics RM0365 Reference Manual page 368

RM0365
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:3 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0
Bites 2:0 Reserved
000: 1.5 ADC clock cycles
001: 2.5 ADC clock cycles
010: 4.5 ADC clock cycles
011: 7.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 61.5 ADC clock cycles
110: 181.5 ADC clock cycles
111: 601.5 ADC clock cycles
(which ensures that no conversion is ongoing).
DocID025202 Rev 7
Analog-to-digital converters (ADC)
368/1080
392