Flash Program And Erase Operations - STMicroelectronics RM0365 Reference Manual

RM0365
Access latency
In order to maintain the control signals to read the Flash memory, the ratio of the prefetch
controller clock period to the access time of the Flash memory has to be programmed in the
Flash access control register with the LATENCY[2:0] bits. This value gives the number of
cycles needed to maintain the control signals of the Flash memory and correctly read the
required data. After reset, the value is zero and only one cycle without additional wait states
is required to access the Flash memory.
DCode interface
The DCode interface consists of a simple AHB interface on the CPU side and a request
generator to the Arbiter of the Flash access controller. The DCode accesses have priority
over prefetch accesses. This interface uses the Access Time Tuner block of the prefetch
buffer.
Flash Access controller
Mainly, this block is a simple arbiter between the read requests of the prefetch/ICode and
DCode interfaces.
DCode interface requests have priority over other requests.
4.2.3

Flash program and erase operations

The STM32F302xx embedded Flash memory can be programmed using in-circuit
programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I
etc.) to download programming data into memory. IAP allows the user to re-program the
Flash memory while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
The program and erase operations are managed through the following seven Flash
registers:
•
Key register (FLASH_KEYR)
•
Option byte key register (FLASH_OPTKEYR)
•
Flash control register (FLASH_CR)
•
Flash status register (FLASH_SR)
•
Flash address register (FLASH_AR)
•
Option byte register (FLASH_OBR)
•
Write protection register (FLASH_WRPR)
An on going Flash memory operation will not block the CPU as long as the CPU does not
access the Flash memory.
On the contrary, during a program/erase operation to the Flash memory, any attempt to read
the Flash memory will stall the bus. The read operation will proceed correctly once the
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