STMicroelectronics RM0365 Reference Manual page 660

RM0365
Bit 8 Reserved, must be kept at reset value.
Bit 7 BIF: Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode, both edges in case gated mode
is selected). It is set when the counter starts or stops when gated mode is selected. It is
cleared by software.
Bit 5 COMIF: COM interrupt flag
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software.
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
If channel CC1 is configured as output: This flag is set by hardware when the counter
matches the compare value. It is cleared by software.
If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared
by software or by reading the TIMx_CCR1 register.
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
– At overflow regarding the repetition counter value (update if repetition counter = 0) and if the
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
– When CNT is reinitialized by a trigger event (refer to
0: No break event occurred
1: An active level has been detected on the break input
0: No trigger event occurred
1: Trigger interrupt pending
0: No COM event occurred
1: COM interrupt pending
refer to CC1IF description
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
UDIS=0 in the TIMx_CR1 register.
UDIS=0 in the TIMx_CR1 register.
control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
General-purpose timers (TIM15/TIM16/TIM17)
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Section 22.5.3: TIM15 slave mode
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