Watchdog Clock; I2S Clock; Clock-Out Capability - STMicroelectronics RM0365 Reference Manual

RM0365
In this configuration:
•
On the STM32F302xB/C, AHB and APB2 prescalers are set to 1, i.e. AHB and APB2
clocks are not divided with respect to the system clock.
•
On the STM32F302x6/8 AHB or APB2 subsystem clocks are not divided by more than
2 cumulatively with respect to the system clock.
9.2.11

Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
9.2.12

I2S clock

The I2S clock can be either the System clock or an external clock provided on I2S_CKIN
pin. The selection of the I2S clock source is performed using bit 23 (I2SSRC) of
RCC_CFGR register.
9.2.13

Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 5 clock signals can be selected as the MCO
clock.
•
LSI
•
LSE
•
SYSCLK
•
HSI
•
HSE
•
PLL clock dividedby 2 on the STM32F302xBxC and PLL clock not divided or divided by
2 on the STM32F302x6/8 and STM32F302xD/E, using the PLLNODIV bit in
RCC_CFGR register
The selection is controlled by the MCO[2:0] bits in the
(RCC_CFGR).
On the STM32F302x6/8 and STM32F302xD/E, the MCO frequency can be reduced by a
configurable divider, controlled by the MCOPRE[2..0] bits of the Clock configuration register
(RCC_CFGR).
DocID025202 Rev 7
Reset and clock control (RCC)
Clock configuration register
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