Tsc Interrupt Enable Register (Tsc_Ier) - STMicroelectronics RM0365 Reference Manual

RM0365
Bit 2 AM: Acquisition mode
This bit is set and cleared by software to select the acquisition mode.
Note: This bit must not be modified when an acquisition is ongoing.
Bit 1 START: Start a new acquisition
This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the
acquisition is complete or by software to cancel the ongoing acquisition.
Bit 0 TSCE: Touch sensing controller enable
This bit is set and cleared by software to enable/disable the touch sensing controller.
Note: When the touch sensing controller is disabled, TSC registers settings have no effect.
19.6.2

TSC interrupt enable register (TSC_IER)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIE: Max count error interrupt enable
This bit is set and cleared by software to enable/disable the max count error interrupt.
Bit 0 EOAIE: End of acquisition interrupt enable
This bit is set and cleared by software to enable/disable the end of acquisition interrupt.
0: Normal acquisition mode (acquisition starts as soon as START bit is set)
1: Synchronized acquisition mode (acquisition starts if START bit is set and when the
selected signal is detected on the SYNC input pin)
0: Acquisition not started
1: Start a new acquisition
0: Touch sensing controller disabled
1: Touch sensing controller enabled
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: Max count error interrupt disabled
1: Max count error interrupt enabled
0: End of acquisition interrupt disabled
1: End of acquisition interrupt enabled
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
DocID025202 Rev 7
Touch sensing controller (TSC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
17 16
Res. Res.
1 0
MCEIE EOAIE
rw rw
448/1080
455