Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - STMicroelectronics RM0365 Reference Manual

RM0365
Bit 2 HSIRDYF: HSI ready interrupt flag
Set by hardware when the HSI clock becomes stable and HSIRDYDIE is set in a response to
setting the HSION (refer to
HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no
interrupt is generated.
Cleared by software setting the HSIRDYC bit.
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
9.4.4

APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res Res Res
15 14 13
USART1
SPI4R
Res
ST
RST
rw rw
1. Available only on STM32F302xB/C/D/E devices.
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: TIM17 timer reset
Set and cleared by software.
Bit 17 TIM16RST: TIM16 timer reset
Set and cleared by software.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
28 27 26 25
Res Res Res Res
12 11 10 9
SPI1
TIM1
Res Res
(1)
RST
RST
rw rw
0: No effect
1: Reset TIM17 timer
0: No effect
1: Reset TIM16 timer
Clock control register (RCC_CR)). When HSION is not set but the
24 23 22
Res Res Res
8 7 6
Res Res Res
DocID025202 Rev 7
Reset and clock control (RCC)
21 20 19 18
TIM17
Res Res Res
RST
rw
5 4 3 2
Res Res Res Res
17 16
TIM16
TIM15
RST
RST
rw rw
1 0
SYS
Res CFG
RST
rw
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