I 2 S Slave Mode - STMicroelectronics RM0365 Reference Manual

RM0365
if the RXNEIE bit is set in SPIx_CR2 register. Depending on the data and channel length
configuration, the audio value received for a right or left channel may result from one or two
receptions into the Rx buffer.
Clearing the RXNE bit is performed by reading the SPIx_DR register.
CHSIDE is updated after each reception. It is sensitive to the WS signal generated by the
2
I S cell.
For more details about the read operations depending on the I
refer to Section 30.7.3: Supported audio
If data are received while the previously received data have not been read yet, an overrun is
generated and the OVR flag is set. If the ERRIE bit is set in the SPIx_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I
transfer cycle properly without initiating a new data transfer. The sequence depends on the
configuration of the data and channel lengths, and on the audio protocol mode selected. In
the case of:
•
16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1)
using the LSB justified mode (I2SSTD = 10)
a)
b)
c)
• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) in
MSB justified, I
respectively)
a)
b)
c)
•
For all other combinations of DATLEN and CHLEN, whatever the audio mode selected
through the I2SSTD bits, carry out the following sequence to switch off the I
a)
b)
c)
Note: The BSY flag is kept low during transfers.
2
30.7.7 I S slave mode
The I2S can be configured as follows:
•
In slave mode for transmission or reception (half-duplex mode using I2Sx)
•
In slave mode transmission and reception (full-duplex mode using I2Sx and I2Sx_ext).
The operating mode is following mainly the same rules as described for the I
configuration. In slave mode, there is no clock to be generated by the I
clock and WS signals are input from the external master connected to the I
There is then no need, for the user, to configure the clock.
The configuration steps to follow are listed below:
2
S, specific actions are required to ensure that the I
Wait for the second to last RXNE = 1 (n – 1)
2
Then wait 17 I S clock cycles (using a software loop)
2
Disable the I S (I2SE = 0)
2
S or PCM modes (I2SSTD = 00, I2SSTD = 01 or I2SSTD = 11,
Wait for the last RXNE
2
Then wait 1 I S clock cycle (using a software loop)
2
Disable the I S (I2SE = 0)
Wait for the second to last RXNE = 1 (n – 1)
2
Then wait one I S clock cycle (using a software loop)
2
Disable the I S (I2SE = 0)
DocID025202 Rev 7
Serial peripheral interface / inter-IC sound (SPI/I2S)
protocols.
2
S standard mode selected,
2
S completes the
2
S:
2
S master
2
S interface. The
2
S interface.
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