Power Control/Status Register (Pwr_Csr) - STMicroelectronics RM0365 Reference Manual

RM0365
8.4.2

Power control/status register (PWR_CSR)

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29 28
Res Res Res Res
15 14 13 12
Res Res Res Res
Bits 31:11 Reserved, must be kept at reset value.
Bit 2 CWUF: Clear wakeup flag.
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)
Bit 1 PDDS: Power down deepsleep.
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status
depends on the LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPDS: Low-power deepsleep.
This bit is set and cleared by software. It works together with the PDDS bit.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
27 26 25
Res Res Res
11 10 9
Res EWUP3 EWUP2 EWUP1
rw rw
Bit 10 EWUP3: Enable WKUP3 pin
This bit is set and cleared by software.
0: WKUP3 pin is used for general purpose I/O. An event on the WKUP3 pin does
not wakeup the device from Standby mode.
1: WKUP3 pin is used for wakeup from Standby mode and forced in input pull
down configuration (rising edge on WKUP3 pin wakes-up the system from
Standby mode).
Note: This bit is reset by a system Reset.
Bit 9 EWUP2: Enable WKUP2 pin
This bit is set and cleared by software.
0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does
not wakeup the device from Standby mode.
1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull
down configuration (rising edge on WKUP2 pin wakes-up the system from
Standby mode).
Note: This bit is reset by a system Reset.
DocID025202 Rev 7
24 23 22 21
Res Res Res Res
8 7 6 5
Res Res Res
rw
Power control (PWR)
20 19 18 17
Res Res Res Res
4 3 2 1
Res Res PVDO SBF
r r
16
Res
0
WUF
r
110/1080
112