STMicroelectronics RM0365 Reference Manual page 151

Reset and clock control (RCC)
Bits 19:18 USART3SW[1:0]: USART3 clock source selection
This bit is set and cleared by software to select the USART3 clock source.
00: PCLK selected as USART3 clock source (default)
01: System clock (SYSCLK) selected as USART3 clock
10: LSE clock selected as USART3 clock
11: HSI clock selected as USART3 clock
Note:
USART3SW[1:0] is not available in the STM32F302x6/8
Bits 17:16 USART2SW[1:0]: USART2 clock source selection
This bit is set and cleared by software to select the USART2 clock source.
00: PCLK selected as USART2 clock source (default)
01: System clock (SYSCLK) selected as USART2 clock
10: LSE clock selected as USART2 clock
11: HSI clock selected as USART2 clock
Note:
USART2SW[1:0] is not available in the STM32F302x6/8
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 TIM17SW: Timer17 clock source selection
Set and reset by software to select TIM17 clock source.
The bit is writable only when the following conditions occur: system clock source is the PLL
and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively.
The bit is reset by hardware when exiting from the previous condition (user must set the bit
again in case of a new switch is required)
0: PCLK2 clock (doubled frequency when prescaled) (default)
1: PLL vco output (running up to 144 MHz)
Note: STM32F302x6/8 and STM32F302xD/E devices only.
Bit 12 Reserved, must be kept at reset value.
Bit 11 TIM16SW: Timer16 clock source selection
Set and reset by software to select TIM16 clock source.
The bit is writable only when the following conditions occur: system clock source is the PLL
and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively.
The bit is reset by hardware when exiting from the previous condition (user must set the bit
again in case of a new switch is required)
0: PCLK2 clock (doubled frequency when prescaled) (default)
1: PLL vco output (running up to 144 MHz)
Note: STM32F302x6/8 and STM32F302xD/E devices only.
Bit 10 TIM15SW: Timer15 clock source selection
Set and reset by software to select TIM15 clock source.
The bit is writable only when the following conditions occur: system clock source is the PLL
and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively.
The bit is reset by hardware when exiting from the previous condition (user must set the bit
again in case of a new switch is required)
0: PCLK2 clock (doubled frequency when prescaled) (default)
1: PLL vco output (running up to 144 MHz)
Note: STM32F302x6/8 and STM32F302xD/E devices only.
Bit 9 Reserved, must be kept at reset value.
151/1080 DocID025202 Rev 7
RM0365