I2S Main Features; Spi/I2S Implementation; Table 161. Stm32F302X6/8 Spi Implementation - STMicroelectronics RM0365 Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
30.3

I2S main features

• Full-duplex communication
•
Half-duplex communication (only transmitter or receiver)
• Master or slave operations
•
8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
•
Data format may be 16-bit, 24-bit or 32-bit
•
Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
•
Programmable clock polarity (steady state)
•
Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave) and Frame Error Flag in reception and transmitter mode (slave only)
•
16-bit register for transmission and reception with one data register for both channel
sides
•
Supported I
–
–
–
–
•
Data direction is always MSB first
•
DMA capability for transmission and reception (16-bit wide)
•
Master clock can be output to drive an external audio component. Ratio is fixed at
256 × F
2
•
I S (I2S2 and I2S3) clock can be derived from an external clock mapped on the
I2S_CKIN pin.
30.4

SPI/I2S implementation

This manual describes the full set of features implemented in SPI1, SPI2 and SPI3.
Hardware CRC calculation
Rx/Tx FIFO
NSS pulse mode
I2S mode
TI mode
1. X = supported.
903/1080
2
S protocols:
2
I S Philips standard
MSB-justified standard (left-justified)
LSB-justified standard (right-justified)
PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
(where F is the audio sampling frequency)
S S

Table 161. STM32F302x6/8 SPI implementation

(1)
SPI
Features
DocID025202 Rev 7
SPI2 SPI3
X
X
X
X
X
RM0365
X
X
X
X
X