Channel-Wise Programmable Sampling Time (Smpr1, Smpr2) - STMicroelectronics RM0365 Reference Manual

Analog-to-digital converters (ADC)
Note: To convert one of the internal analog channels, the corresponding analog sources must first
be enabled by programming bits VREFEN, TSEN or VBATEN in the ADCx_CCR registers.
It is possible to organize the conversions in two groups: regular and injected. A group
consists of a sequence of conversions that can be done on any channel and in any order.
For instance, it is possible to implement the conversion sequence in the following order:
ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0, ADC_IN2, ADC_IN2, ADC_IN15.
•
A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADCx_SQR registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADCx_SQR1 register.
•
An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADCx_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADCx_JSQR register.
ADCx_SQR registers must not be modified while regular conversions can occur. For this,
the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to
Section 15.3.17: Stopping an ongoing conversion (ADSTP,
It is possible to modify the ADCx_JSQR registers on-the-fly while injected conversions are
occurring. Refer to
15.3.12

Channel-wise programmable sampling time (SMPR1, SMPR2)

Before starting a conversion, the ADC must establish a direct connection between the
voltage source under measurement and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the embedded
capacitor to the input voltage level.
Each channel can be sampled with a different sampling time which is programmable using
the SMP[2:0] bits in the ADCx_SMPR1 and ADCx_SMPR2 registers. It is therefore possible
to select among the following sampling time values:
•
SMP = 000: 1.5 ADC clock cycles
•
SMP = 001: 2.5 ADC clock cycles
•
SMP = 010: 4.5 ADC clock cycles
•
SMP = 011: 7.5 ADC clock cycles
•
SMP = 100: 19.5 ADC clock cycles
•
SMP = 101: 61.5 ADC clock cycles
•
SMP = 110: 181.5 ADC clock cycles
•
SMP = 111: 601.5 ADC clock cycles
The total conversion time is calculated as follows:
Tconv = Sampling time + 12.5 ADC clock cycles
Example:
With F
Tconv = (1.5 + 12.5) ADC clock cycles = 14 ADC clock cycles = 0.194 µs (for fast
channels)
The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for
regular conversion).
301/1080
Section 15.3.21: Queue of context for injected conversions
= 72 MHz and a sampling time of 1.5 ADC clock cycles:
ADC_CLK
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RM0365