Timx Prescaler (Timx_Psc); Timx Auto-Reload Register (Timx_Arr) - STMicroelectronics RM0365 Reference Manual

General-purpose timers (TIM2/TIM3/TIM4)
Bit 31 Value depends on IUFREMAP in TIMx_CR1.
Bits 30:16 CNT[30:16]: Most significant part counter value (on TIM2 )
Bits 15:0 CNT[15:0]: Least significant part of counter value
21.4.11

TIMx prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
21.4.12

TIMx auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0xFFFF FFFF
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2 )
Bits 15:0 ARR[15:0]: Low Auto-reload Prescaler value
613/1080
If UIFREMAP = 0
CNT[31]: Most significant bit of counter value (on TIM2 )
Reserved on other timers
If UIFREMAP = 1
UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register
12 11 10 9
rw rw rw rw
The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
28 27 26 25
ARR[31:16] (depending on timers)
rw rw rw rw
12 11 10 9
rw rw rw rw
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 21.3.1: Time-base unit on page 552
and behavior.
The counter is blocked while the auto-reload value is null.
8 7 6
PSC[15:0]
rw rw rw
24 23 22
rw rw rw
8 7 6
ARR[15:0]
rw rw rw
DocID025202 Rev 7
5 4 3 2
rw rw rw rw
/ (PSC[15:0] + 1).
CK_PSC
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
for more details about ARR update
RM0365
1 0
rw rw
17 16
rw rw
1 0
rw rw