STMicroelectronics RM0365 Reference Manual page 888

RM0365
Bit 12 OVRDIS: Overrun Disable
Note: This control bit allows checking the communication flow without reading the data.
Bit 11 ONEBIT: One sample bit method enable
Note: ONEBIT feature applies only to data bits, It does not apply to Start bit.
Bit 10 CTSIE: CTS interrupt enable
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
Bit 9 CTSE: CTS enable
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
Bit 8 RTSE: RTS enable
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
Bit 7 DMAT: DMA enable transmitter
Bit 6 DMAR: DMA enable receiver
Universal synchronous asynchronous receiver transmitter (USART)
This bit is used to disable the receive overrun detection.
0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
the ORE flag is not set and the new received data overwrites the previous content of the
USART_RDR register.
This bit can only be written when the USART is disabled (UE=0).
This bit allows the user to select the sample method. When the one sample bit method is
selected the noise detection flag (NF) is disabled.
0: Three sample bit method
1: One sample bit method
This bit can only be written when the USART is disabled (UE=0).
0: Interrupt is inhibited
1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register
hardware to '0'. Please refer to
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to 0). If
the CTS input is de-asserted while data is being transmitted, then the transmission is
completed before stopping. If data is written into the data register while CTS is de-asserted,
the transmission is postponed until CTS is asserted.
This bit can only be written when the USART is disabled (UE=0)
hardware to '0'. Please refer to
0: RTS hardware flow control disabled
1: RTS output enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted.
The RTS output is asserted (pulled to 0) when data can be received.
This bit can only be written when the USART is disabled (UE=0).
hardware to '0'. Please refer to
This bit is set/reset by software
1: DMA mode is enabled for transmission
0: DMA mode is disabled for transmission
This bit is set/reset by software
1: DMA mode is enabled for reception
0: DMA mode is disabled for reception
DocID025202 Rev 7
Section 29.4: USART implementation on page
Section 29.4: USART implementation on page
Section 29.4: USART implementation on page
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