Reset and clock control (RCC)
9
Reset and clock control (RCC)
9.1
Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.
9.1.1
Power reset
A power reset is generated when one of the following events occurs:
1.
Power-on/power-down reset (POR/PDR reset)
2.
When exiting Standby mode
A power reset sets all registers to their reset values except the RTC domain (see
on page
9.1.2
System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the RTC domain (see
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset)
2.
Window watchdog event (WWDG reset)
3.
Independent watchdog event (IWDG reset)
4.
A software reset (SW reset) (see
5.
Low-power management reset (see
6.
Option byte loader reset (see
7.
A power reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
113/1080
97).
Section 9.4.10: Control/status register
DocID025202 Rev 7
Software
reset)
Low-power management
Option byte loader
reset)
(RCC_CSR)).
RM0365
Figure 8
Figure 8 on page
97).
reset)
Need help?
Do you have a question about the RM0365 and is the answer not in the manual?